The present invention relates generally to the field of instruction processing and more particularly to mapping logical resources to physical resources in an instruction processing pipeline.
The instruction set architecture of many CPUs references a set of registers which are used to stage data between memory and the functional units on the chip. In simpler CPUs, these architectural registers correspond one-for-one to the entries in a physical register file within the CPU. Some advanced CPUs have a pool of physical registers that are assigned to logical registers on an as-needed basis. Such CPUs may map a logical register identifier to a physical register index via a mapper.